"Non-Heuristic Optimization and Synthesis of Parallel-Prefix Adders"

R. Zimmermann

Abstract
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The class of parallel-prefix adders comprises the most area-delay efficient
adder architectures -- such as the ripple-carry, the carry-increment, and the
carry-lookahead adders -- for the entire range of possible area-delay
trade-offs. The generic description of these adders as prefix structures allows
their simple and consistent area optimization and synthesis under given timing
constraints, including non-uniform input and output signal arrival times. This
paper presents an efficient non-heuristic algorithm for the generation of
size-optimal parallel-prefix structures under arbitrary depth constraints.