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Lectures
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VLSI III: Fabrikation und Verifikation von hochintegrierten Schaltungen

VLSI III: Fabrication and Verification of Highly Integrated Circuits

EE/CS 8th Sem.

Whereas the other two courses deal with design aspects of VLSI circuits, this one addresses manufacturing, testing, physical analysis, and packaging issues, such as: Effects of fabrication defects, abstraction from physical to transistor- and gate-level fault models, fault grading of large ASICs. Generation of efficient test vector sets, enhancement of testability by built-in self-test techniques. Modern IC testers: Architectures and application. New deep-submicron CMOS processes with multi metal levels and the physical analysis of their devices. Packaging problems and solutions.

Exercises teach students how to use CAE/CAD software and automatic test equipment for verifying ASICs after fabrication. Students that submitted a design for manufacturing at the end of the 7th semester do so on their own circuits. Physical analysis methods with professional equipment (AFM, DLTS) complement this training.

Detailed information for the actual semester

Last change:  6 September 2005    Author:  Norbert Felber