Series in Microelectronics: Volume 157

Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems

Abstract

This thesis briefly outlines the development of a novel design methodology for Globally-Asynchronous Locally-Synchronous (GALS) architectures that was done in the rst phase of the GALS project and then concentrates on the specication and implementation of appropriate on-chip interconnection structures for complexer GALS systems.

GALS is an approach to VLSI system design that holds the promise of combining the advantages of both synchronous and asynchronous design methodologies. A GALS system employs a self-timed communication scheme between independently clocked circuit blocks, termed locally-synchronous islands. This islands are designed in accordance to proven synchronous clocking disciplines and along a well established design-flow. Any asynchronous circuitry necessary for coordinating the clock-driven with the self-timed operation is conned to self-timed wrappers arranged around each locally-synchronous island. A synchronous island together with the surrounding wrapper then forms a GALS module. To avoid synchronisation failure, all data inputs from other GALS modules have to be synchronised to the local clock. To achieve this, the local clock is paused when data and sampling clock edges occur too close to each other.

The decreasing feature size of modern CMOS technologies allows for integrating more and more functionality on a single chip, referred to as System-on-a-Chip (SoC). This complexity is only manageable if independent subsystems are developed individually before being brought together in the nal stages of development. As technology scales down, system-wide communication becomes one of the key compoviiV8V8 nents of modern ultra-deep submicron SoC designs, as it entails the main design constraints in terms of system performance, power consumption, robustness, and cost.

So far, all GALS approaches were restricted to point-to-point data transfer channels. Multi-point data exchange has become key necessity of a modern SoC design as point-to-point links alone do not provide the necessary modularity and extendibility. The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying the GALS techniques to SoC design. The GALS point-to-point data exchange channels have therefore been extended towards more versatile multi-point interconnection schemes while preserving the modular approach and the selftimed operation.

Three interconnection structures with distinct topologies were developed, implemented, and compared:

• MOdular GaLs Interconnect (MOGLI), a shared bus solution with both central arbitration and address decoding.
• A ring topology, named Self-Timed Ring for GALS (STRING). With STRING, several GALS modules are connected with a circular path. Dedicated self-timed ring transceivers free the local islands from managing en route trac.
• SWItching Network for GALS (SWING), a switch matrix built from self-timed crossbar elements.

The three interconnection solutions together with variants thereof have been validated by implementing a complex multiprocessor array on silicon. While their performance measure up to the commercial synchronous counterparts, their main advantage is clearly the modularity they oer and the timing closure that is inherently guaranteed at their interfaces.

Authors

• Thomas Villiger

Ordering Information

• Hartung Gorre Verlag