ESSCIRC 2005:
ESSCIRC 2005, 31st European Solid-State Circuits Conference, Grenoble, France.
Improving DPA Security by Using Globally-Asynchronous Locally-Synchronous Systems
Abstract
Side channel analysis attacks, and particularly Differential Power
Analysis (DPA), pose a serious threat to cryptographic security. This
is partly because the synchronous operation of traditional cipher
hardware affords a fairly good correlation between the abstract power
model used during analysis and the physical circuit under attack.
As opposed to this, the globally-asychronous locally-synchronous (GALS)
AES cipher circuit discussed in this paper combines operation reordering
and unpredictable latencies with three asynchrous clock domains and
self-varying clock cycle times. Attackers are further confused by
having functional units process random dummy data when idle. The design
fabricated in a 0.25 um CMOS technology comprises 39,000
gate-equivalents, occupies approximately 1 sqmm and achieves
a peak throughput of more than 256 Mb/s.
Authors
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