ACiD2001:
First ACiD-WG Workshop of the European Commission's Fifth Framework Programme
Neuchatel, Switzerland
A Globally-Asynchronous Locally-Synchronous VLSI Circuit for the SAFER Cryptoalgorithm
Abstract
GALS makes it possible to take advantage of
the industry-standard synchronous design methodology
within individual clock domains and of self-timed operation
across clock boundaries. A price to pay is the extra
circuitry in the wrappers and the need for unorthodox
subcircuits. For sake of economy and energy efficiency,
grain size is much larger than in fully self-timed circuits.
To the best of our knowledge, this work is the first
to demonstrate GALS operation in actual silicon for a
circuit of substantial complexity. The ASIC serving as
a test vehicle is capable of ciphering and deciphering
data following the SAFER SK-128 cryptoalgorithm, a
popular block cipher with a block size of 64bit and key
length 128. The ciphering modes supported include the
ISO 10116 modes ECB (no feedback), CBC, OFB, and
CFB (all including feedback) with up to 12 rounds.
Authors
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