F. K. Gurkaynak, S. Oetiker, H. Kaeslin, N. Felber and W. Fichtner: "GALS at ETH Zurich: Success or Failure ?", Proceedings of the Twelfth IEEE International Symposium on Asynchronous Circuits and Systems, Grenoble France, pp. xxx-yyy, March 13-15, 2006.

F. K. Gurkaynak, "GALS System Design: Side Channel Attack Secure Cryptographic Accelerators", Series in Microelectronics Volume 168, Hartung Gorre Verlag, ISBN-3-86628-065-3, 2006.

2005

F. K. Gurkaynak, S. Oetiker, N. Felber, H. Kaeslin and W. Fichtner: "Improving DPA Security by Using Globally-Asynchronous Locally-Synchronous Systems", ESSCIRC 2005, 31st European Solid-State Circuits Conference, pp. 407-411, 12-16.9.2005, Grenoble, France

F. K. Gurkaynak, S. Oetiker, N. Felber, H. Kaeslin and W. Fichtner: "Design Challenges for a Differential Power Analysis Aware GALS based AES Crypto-ASIC", Second International Workshop on Formal Methods For Globally Asynchronous Locally Synchronous (GALS) Architectures FMGALS 2005, Verona, Italy, 15 July 2005.

T. Villiger, "Multi-point Interconnects for Globally-Asynchronous Locally-Synchronous Systems", Series in Microelectronics Volume 157, Hartung Gorre Verlag, ISBN-3-86628-003-3, 2005.

2004

F. K. Gurkaynak, S. Oetiker, N. Felber, H. Kaeslin and W. Fichtner: "Is there hope for GALS in the Future?", Handouts of the Fourth Asynchronous Circuit Design Workshop, ACiD 2004, Turku, Finland, June 28-29 2004.

2003

F. K. Gurkaynak, S. Oetiker, T. Villiger, N. Felber, H. Kaeslin, and W. Fichtner: "On the GALS Design Methodology of ETH Zurich", Proceedings of the Formal Methods For Globally Asynchronous Locally Synchronous (GALS) Architecture FMGALS2003, Pisa, Italy. pp 32-41, September 13 2003.

T. Villiger, H. Kaeslin, F. K. Gurkaynak, S. Oetiker, and W. Fichtner: "Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems", Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems, Vancouver, BC, Canada, pp. 141-150 , May 12-16 2003.

S. Oetiker, F. K. Gurkaynak, T. Villiger, H. Kaeslin, N. Felber and W. Fichtner: "Design flow for a 3-million transistor GALS test chip", Handouts of the Third Asynchronous Circuit Design Workshop, ACiD 2003, Heraklion, Greece, January 27-28 2003.

2002

F. K. Gurkaynak, T. Villiger, S. Oetiker:"An Introduction to the GALS Methodology at ETH Zurich", presented at the CANDE (Computer-Aided Network DEsign) Workshop 2002, Anchorage, Alaska

F. K. Gurkaynak, T. Villiger, S. Oetiker, N. Felber, H. Kaeslin and W. Fichtner: "A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems", Proceedings of the Eighth IEEE International Symposium on Asynchronous Circuits and Systems, Manchester UK, pp. 166-174, April 8-11, 2002.

T. Villiger, F. K. Gurkaynak, S. Oetiker, H. Kaeslin, N. Felber and W. Fichtner: "Multi-point Interconnect for Globally-Asynchronous Locally Synchronous Systems", Handouts of the Second Asynchronous Circuit Design Workshop, ACiD 2002, Munich, Germany, January 28-29 2002.

S. Oetiker, T. Villiger, F. K. Gurkaynak, H. Kaeslin, N. Felber and W. Fichtner: "High Resolution Clock Generators for Globally-Asynchronous Locally-Synchronous Designs", Handouts of the Second Asynchronous Circuit Design Workshop, ACiD 2002, Munich, Germany, January 28-29 2002.

2001

J. Muttersbach, "Globally-Asynchronous Locally-Synchronous Architectures for VLSI Systems", Series in Microelectronics Volume 120, Hartung Gorre Verlag, ISBN-3-89649-724-3, 2001.

T. Villiger, J. Muttersbach, H. Kaeslin, N. Felber, W. Fichtner: "A Globally-Asynchronous Locally-Synchronous VLSI Circuit for the SAFER Cryptoalgorithm", Handouts of the First ACiD-WG Workshop of the European Commission's Fifth Framework Programme, Neuchatel, Switzerland, February 12-13, 2001.

2000

J. Muttersbach, T. Villiger, W. Fichtner: "Practical Design of Globally-Asynchronous Locally-Synchronous Systems", Proceedings of the Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC'2000, Eilat, Israel, pp. 52-59, April 2-6, 2000.

1999

J. Muttersbach, T. Villiger, H. Kaeslin, N. Felber, W. Fichtner: "Globally-Asynchronous Locally-Synchronous Architectures to Simplify the Design of On-chip Systems", Proceedings of the twelfth Annual IEEE International ASIC/SOC Conference, Washington DC, USA, pp.317-321, September 15-18, 1999.